1. Field of the Invention
The present invention relates to a voltage detecting circuit. More specifically, the invention relates to a voltage detecting circuit configured to detect that voltage applied to an input terminal exceeds preset trigger voltage.
2. Description of the Prior Art
One proposed structure of the voltage detecting circuit includes a reference voltage generating circuit having an NMOS depletion transistor that a drain thereof is connected with a power supply terminal and a source thereof is connected with a gate thereof, and an NMOS enhancement transistor that a drain and a gate thereof are connected with the drain of the NMOS depletion transistor and a source thereof is connected to ground. The voltage detecting circuit also includes a comparator configured to compare detecting voltage that is obtained by dividing input voltage by two resistances with reference voltage that is output from the reference voltage generating circuit, and outputs a signal that is based on comparative result of the comparator (see, for example, patent document 1) . In this prior art voltage detecting circuit, operation described above enables to detect that detected voltage based on the voltage of the input terminal becomes higher than the reference voltage.
Patent Document 1: Japanese Patent Laid-Open No. 2009-198476
Because of necessity for the reference voltage circuit and the comparator, in the above voltage detecting circuit, the size of circuit is comparatively large. In the reference voltage circuit of the above voltage detecting circuit, the gate of the NMOS depletion transistor is connected with the drain thereof, and the gate of the NMOS enhancement transistor is connected with the drain thereof. Because of these connections, current continues to flow from the NMOS depletion transistor to the NMOS enhancement transistor when voltage is applied to the power supply terminal, and power consumption becomes comparatively large.